1. Field of the Invention
This invention relates to a method and apparatus for the test-cause generation which, for example, systematically performs the function test for a logical device, and particularly to a method and apparatus for the test-cause generation capable of reducing the processing time without sacrificing the test accuracy in partial test-cause generation, which conventionally has consumed a lot of time when there are intricate boolean functions between inputs and outputs.
2. Description of the Prior Art
The conventional test-cause generation method, which generates test-causes for use in testing a logical device whose functions are expressed by state transitions and combinatorial logics, such as a computer, and thus in testing a computer program, is designed to transform the boolean functions expressed in decision tables into cause-effect graphs having the equivalent logical meaning and generate partial test-causes in one state based on the boolean functions expressed in the cause-effect graphs, as disclosed for example in Japanese Patent Unexamined Publication No. 59-151248. In this case, the final test-cause is produced by combining partial test-causes generated for each state.
However, the above-mentioned conventional technique has expended an extremely long time in generating partial test causes when the input-output correspondence has intricate boolean functions, and the test-cause generation process must have been aborted in some case, due to the following reason.
(1) The cause-effect graph is used for expressing a boolean function, necessitating the constraint conditions for eliminating infeasible combinations, and this check process needs time.
(2) The test pattern generation algorithm oriented to hardware circuits is used for partial test-cause generation, and it takes a large number of trials in generating a consistent test pattern when a combination out of the constraint conditions is removed.